Formal Verification of Continuous Models of Analog Circuits

The goal of verifying an analog circuit is to make sure that the implementation of the circuit exhibits the desired behavior. Traditionally, analog circuits are analyzed using simulation techniques. However, simulation results cannot be termed as 100% accurate due to the approximations introduced by using computer arithmetics, such as floating or fixed point numbers, for constructing computer based models of the continuous analog circuits. Moreover, the circuits are analyzed for some specific test cases only since exhaustive simulation is not possible due to the continuous nature of inputs. Due to these limitations, more rigorous and accurate analysis techniques for analyzing analog circuits are actively sought and formal verification., i.e., a computer based mathematical analysis technique, offers a promising solution [5]. The rigorous exercise of developing a mathematical model for the given system and analyzing this model using mathematical reasoning usually increases the chances for catching subtle but critical design errors that are often ignored by simulation. However, to the best of our knowledge, all the existing formal verification approaches work with abstracted discretized models of analog circuits (e.g., [3],[2]). This is mainly because of the inability to model and analyze continuous systems by the widely used formal verification techniques, such as model checking or automated theorem proving. Thus, despite the inherent soundness of formal verification methods, such analysis cannot be termed as absolutely accurate. We propose to use higher-order-logic theorem proving in order to formally verify continuous models of analog circuits. Higher-order logic is a system of deduction with a precise semantics and, due to its high expressiveness, can be used to describe any mathematical relationship. We argue that the high expressibility of higher-order logic can be leveraged upon to formalize the continuous models of analog circuit implementations and their desired specifications. Their equivalence can then be verified within the sound core of a theorem prover. Due to the high expressibility of higher-order logic, the proposed approach is very flexible in terms of analyzing a variety of analog circuits and reasoning about their generic properties. There are two main challenges in the proposed approach. Firstly, due to the undecidable nature of higher-order logic, the Fig. 1. Proposed Methodology for the Formal Verification of AMS circuits